1. Field of Use
This invention pertains to data processing systems and more particularly to distributed bus priority systems.
2. Prior Art
There are a variety of methods and apparatuses for interconnecting the different unit controllers of a data processing system for transmitting and receiving requests over a common bus. The transfer of requests proceeds either over synchronous or asynchronous generated bus transfer cycles of operation.
U.S. Pat. Nos. 4,030,075 and 4,096,569, assigned to the same assignee as named herein, are illustrative of an asynchronous bus system. These systems have units which are coupled in a priority network which is distributed along the system bus.
In U.S. Pat. No. 4,096,569, the priority logic circuits of the distributed tie-breaking network grants bus cycles and resolves simultaneous requests to use the bus on the basis of a unit's physical position on the bus with the lowest priority being given to the last unit on the bus located at the opposite end of the bus. U.S. Pat. No. 4,559,595 discloses an improvement to the priority logic circuits of U.S. Pat. No. 4,096,569. The priority logic circuits are modified to allow the lowest priority (i.e., the last unit) to be physically at other than its lowest priority position.
In U.S. Pat. Nos. 4,493,036 and 4,600,992, priority resolver logic circuits are provided within a main memory to resolve possible conflicts between competing requests for access to memory.
These prior art arrangements have necessitated that certain types of units, such as central subsystem (CSS) units and memories, be positioned in a particular manner. It has been the practice that in order to place CSS units in both top and bottom priority positions, it was necessary to have their bus request circuits capable of making both high an low priority requests.
In such multiprocessor systems, it is desirable to also include a high speed bus which connects the CSS units and memory subsystems for high speed data transfers. In order to achieve maximum performance, it is essential to have the CSS units and memory subsystems positioned as close to each other as possible. It is also important on an asynchronous bus to position units that produce substantial bus traffic close to the high priority end of the bus, because bus cycles are shorter at those positions. This requirement made it difficult to achieve the desired performance requirements with prior art distributed priority networks.
Accordingly, it is a primary object of the present invention to provide a distributed bus priority network which enables the tight coupling of both central and memory subsystems.
A further object of the present invention is to provide a distributed bus priority system bus in which certain types of subsystems can be positioned anywhere along such system bus.